Most electronic devices require a clock signal to synchronize operations of its internal components with each other. This clock signal is commonly referred to as the system clock, and can be provided by a crystal oscillator having a fixed frequency. Telecommunication devices also require clock signals for transmission and reception of RF signals in addition to a system clock.
Advances in circuit design and semiconductor manufacturing techniques have increased the maximum operating frequency of high performance electronic devices. For example, current Intel Pentium class microprocessors can run at a system clock frequency between 1 GHz and 2 GHz.
Unfortunately, some components of an electronic device will only operate at a maximum frequency that is well below the desired system clock frequency. Although different components will operate with different clock frequencies, all the components of the electronic device must operate synchronously with each other. It is not possible to include separate crystal oscillators in the electronic device because it is impractical to synchronize all the oscillators to the same system clock edges. Furthermore, the addition of more crystal oscillators increases the size of the electronic device, an undesirable attribute of portable devices. Hence on chip frequency divider circuits are used to convert the system clock signal to lower frequencies.
Generally, a frequency divider circuit removes a fixed number of cycles, or pulses, from the incoming system clock signal. For example, a divide-by-2 frequency divider that receives a 10 MHz signal will provide a 5 MHz output. Therefore different components of the electronic device can operate at different speeds, but all synchronized to the system clock and as a result, with each other. For wireless devices, the ability to convert the system clock signal to different frequencies enables its compatibility with regulatory requirements for different frequency bands and enables the device to do so in a cost effective manner, as well as enabling frequency translation of signals in systems with multiple intermediate (IF) frequencies, synchronized calibration, shared clocks between different circuits.
Wireless devices with tri-band transceivers, such as GSM frequency bands for example, require a local oscillator signal in the RF receiver down-conversion mixer and the RF transmitter up-conversion mixer in order to receive and/or send RF signals. A divide by three factor of the system clock signal enables the use of a single local oscillator to support for example, the three GSM frequency bands. Frequency dividers of the art can divide the incoming frequency by any even or odd factor, and typically consists of a chain of flip-flop circuits arranged in a ring such that its output is fed-back to its input. Traditional divide-by-3 or other odd numbered frequency dividers are not capable of producing a lowered frequency having a 50% duty cycle. A 50% duty cycle is highly desired in RF applications to reduce spurious outputs from the device as well as to reduce the sensitivity of the device to spurious inputs. Furthermore, a 50% duty cycle is desired because when driving mixers, the worst-case noise is seen when the mixer switches are both on (i.e. during the transition period). A 50% duty cycle minimizes the average noise and hence reduces the noise figure of the mixer.
Other frequency dividers require combinational logic between each flip-flop stage which is difficult to implement in RF applications due to the voltage headroom constraints and bandwidth limitations that can limit performance of the device. Other solutions are too complex and are thus not cost effective implement.
It is therefore desirable to provide a frequency divider circuit that provides a reduced clock frequency having a 50% duty cycle which does not require the use of combinational logic between flip-flop stages, is simple and cost effective to implement.